ADC DMA packet controllerΒΆ

TerosHDL

Entity: adc_dma_packet_controller

  • File: adc_dma_packet_controller.vhd

Diagram

integer DMA_LENGTH_WIDTH std_logic ADCxN_clk std_logic ADCxN_reset std_logic_vector(DMA_LENGTH_WIDTH-1 downto 0) DMA_x_length std_logic DMA_x_length_valid std_logic fifo_wr_xfer_req std_logic adc_enable_0 std_logic adc_valid_0 std_logic_vector(15 downto 0) adc_data_0 std_logic adc_enable_1 std_logic adc_valid_1 std_logic_vector(15 downto 0) adc_data_1 std_logic adc_enable_2 std_logic adc_valid_2 std_logic_vector(15 downto 0) adc_data_2 std_logic adc_enable_3 std_logic adc_valid_3 std_logic_vector(15 downto 0) adc_data_3 std_logic adc_overflow std_logic fwd_adc_enable_0 std_logic fwd_adc_valid_0 std_logic_vector(15 downto 0) fwd_adc_data_0 std_logic fwd_adc_enable_1 std_logic fwd_adc_valid_1 std_logic_vector(15 downto 0) fwd_adc_data_1 std_logic fwd_adc_enable_2 std_logic fwd_adc_valid_2 std_logic_vector(15 downto 0) fwd_adc_data_2 std_logic fwd_adc_enable_3 std_logic fwd_adc_valid_3 std_logic_vector(15 downto 0) fwd_adc_data_3 std_logic fwd_adc_overflow

Generics

Generic name Type Value Description
DMA_LENGTH_WIDTH integer 24 Parameter defining the current DMA bandwidth defines the width of transfer length control register in bits; limits the maximum length of the transfers to 2^DMA_LENGTH_WIDTH (e.g., 2^24 = 16M)

Ports

Port name Direction Type Description
ADCxN_clk in std_logic ADC clock signal xN [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADCxN_reset in std_logic ADC high-active reset signal (mapped to the ADC clock xN domain [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
DMA_x_length in std_logic_vector(DMA_LENGTH_WIDTH-1 downto 0) Signal indicating the number of samples comprising the current DMA transfer [@ADCxN_clk]
DMA_x_length_valid in std_logic Valid signal for 'DMA_x_length' [@ADCxN_clk]
fifo_wr_xfer_req in std_logic Signal from DMA core indicating that the new DMA requested is being processed and the core is ready to receive new data
adc_enable_0 in std_logic Enable signal for ADC data port 0
adc_valid_0 in std_logic Valid signal for ADC data port 0
adc_data_0 in std_logic_vector(15 downto 0) ADC parallel data port 0 [16-bit I samples, Rx antenna 1]
adc_enable_1 in std_logic Enable signal for ADC data port 1
adc_valid_1 in std_logic Valid signal for ADC data port 1
adc_data_1 in std_logic_vector(15 downto 0) ADC parallel data port 1 [16-bit Q samples, Rx antenna 1]
adc_enable_2 in std_logic Enable signal for ADC data port 2
adc_valid_2 in std_logic Valid signal for ADC data port 2
adc_data_2 in std_logic_vector(15 downto 0) ADC parallel data port 2 [16-bit I samples, Rx antenna 2]
adc_enable_3 in std_logic Enable signal for ADC data port 3
adc_valid_3 in std_logic Valid signal for ADC data port 3
adc_data_3 in std_logic_vector(15 downto 0) ADC parallel data port 3 [16-bit Q samples, Rx antenna 2]
adc_overflow in std_logic Overflow signal indicating that the DMA request was late
fwd_adc_enable_0 out std_logic Enable signal for ADC data port 0
fwd_adc_valid_0 out std_logic Valid signal for ADC data port 0
fwd_adc_data_0 out std_logic_vector(15 downto 0) ADC parallel data port 0 [16-bit I samples, Rx antenna 1]
fwd_adc_enable_1 out std_logic Enable signal for ADC data port 1
fwd_adc_valid_1 out std_logic Valid signal for ADC data port 1
fwd_adc_data_1 out std_logic_vector(15 downto 0) ADC parallel data port 1 [16-bit Q samples, Rx antenna 1]
fwd_adc_enable_2 out std_logic Enable signal for ADC data port 2
fwd_adc_valid_2 out std_logic Valid signal for ADC data port 2
fwd_adc_data_2 out std_logic_vector(15 downto 0) ADC parallel data port 2 [16-bit I samples, Rx antenna 2]
fwd_adc_enable_3 out std_logic Enable signal for ADC data port 3
fwd_adc_valid_3 out std_logic Valid signal for ADC data port 3
fwd_adc_data_3 out std_logic_vector(15 downto 0) ADC parallel data port 3 [16-bit Q samples, Rx antenna 2]
fwd_adc_overflow out std_logic Overflow signal indicating that the DMA request was late

Instantiations

  • fifo_out_buffer_inst: fifo_out_buffer