DAC FIFO timestamp enablerΒΆ

TerosHDL

Entity: dac_fifo_timestamp_enabler

  • File: dac_fifo_timestamp_enabler.vhd

Diagram

integer PARAM_DMA_LENGTH_WIDTH boolean PARAM_BYPASS integer PARAM_BUFFER_LENGTH integer PARAM_MAX_DMA_PACKET_LENGTH boolean PARAM_DMA_LENGTH_IN_HEADER boolean PARAM_TWO_ANTENNA_SUPPORT string PARAM_MEM_TYPE boolean PARAM_x1_FPGA_SAMPLING_RATIO std_logic s_axi_aclk std_logic s_axi_aresetn std_logic DACxN_clk std_logic DACxN_reset std_logic DAC_clk_division std_logic_vector(63 downto 0) current_lclk_count std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0) DMA_x_length std_logic DMA_x_length_valid std_logic_vector(15 downto 0) dac_data_0 std_logic_vector(15 downto 0) dac_data_1 std_logic_vector(15 downto 0) dac_data_2 std_logic_vector(15 downto 0) dac_data_3 std_logic dac_fifo_unf std_logic dac_enable_0 std_logic dac_valid_0 std_logic dac_enable_1 std_logic dac_valid_1 std_logic dac_enable_2 std_logic dac_valid_2 std_logic dac_enable_3 std_logic dac_valid_3 std_logic s00_axi_aclk std_logic s00_axi_aresetn std_logic DAC_FSM_status_read std_logic fwd_dac_enable_0 std_logic fwd_dac_valid_0 std_logic_vector(15 downto 0) fwd_dac_data_0 std_logic fwd_dac_enable_1 std_logic fwd_dac_valid_1 std_logic_vector(15 downto 0) fwd_dac_data_1 std_logic fwd_dac_enable_2 std_logic fwd_dac_valid_2 std_logic_vector(15 downto 0) fwd_dac_data_2 std_logic fwd_dac_enable_3 std_logic fwd_dac_valid_3 std_logic_vector(15 downto 0) fwd_dac_data_3 std_logic fwd_dac_fifo_unf std_logic DAC_late_flag std_logic DAC_new_late std_logic_vector(31 downto 0) DAC_FSM_status std_logic DAC_FSM_new_status

Generics

Generic name Type Value Description
PARAM_DMA_LENGTH_WIDTH integer 24
PARAM_BYPASS boolean false
PARAM_BUFFER_LENGTH integer 8
PARAM_MAX_DMA_PACKET_LENGTH integer 16000
PARAM_DMA_LENGTH_IN_HEADER boolean false
PARAM_TWO_ANTENNA_SUPPORT boolean false
PARAM_MEM_TYPE string "ramb36e2"
PARAM_x1_FPGA_SAMPLING_RATIO boolean false

Ports

Port name Direction Type Description
s_axi_aclk in std_logic
s_axi_aresetn in std_logic
DACxN_clk in std_logic
DACxN_reset in std_logic
DAC_clk_division in std_logic
current_lclk_count in std_logic_vector(63 downto 0)
DMA_x_length in std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0)
DMA_x_length_valid in std_logic
dac_data_0 in std_logic_vector(15 downto 0)
dac_data_1 in std_logic_vector(15 downto 0)
dac_data_2 in std_logic_vector(15 downto 0)
dac_data_3 in std_logic_vector(15 downto 0)
dac_fifo_unf in std_logic
dac_enable_0 in std_logic
dac_valid_0 in std_logic
dac_enable_1 in std_logic
dac_valid_1 in std_logic
dac_enable_2 in std_logic
dac_valid_2 in std_logic
dac_enable_3 in std_logic
dac_valid_3 in std_logic
fwd_dac_enable_0 out std_logic
fwd_dac_valid_0 out std_logic
fwd_dac_data_0 out std_logic_vector(15 downto 0)
fwd_dac_enable_1 out std_logic
fwd_dac_valid_1 out std_logic
fwd_dac_data_1 out std_logic_vector(15 downto 0)
fwd_dac_enable_2 out std_logic
fwd_dac_valid_2 out std_logic
fwd_dac_data_2 out std_logic_vector(15 downto 0)
fwd_dac_enable_3 out std_logic
fwd_dac_valid_3 out std_logic
fwd_dac_data_3 out std_logic_vector(15 downto 0)
fwd_dac_fifo_unf out std_logic
s00_axi_aclk in std_logic
s00_axi_aresetn in std_logic
DAC_late_flag out std_logic
DAC_new_late out std_logic
DAC_FSM_status out std_logic_vector(31 downto 0)
DAC_FSM_new_status out std_logic
DAC_FSM_status_read in std_logic

Instantiations

  • synchronizer_frame_storing_start_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_dma_xlength_applied_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_timestamp_header_value_mem0_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_timestamp_header_value_mem1_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_timestamp_header_value_mem2_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_timestamp_header_value_mem3_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_num_samples_mem0_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_num_samples_mem1_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_num_samples_mem2_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_num_samples_mem3_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_PS_DAC_RAMB_write_index_mem0_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_PS_DAC_RAMB_write_index_mem1_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_PS_DAC_RAMB_write_index_mem2_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_PS_DAC_RAMB_write_index_mem3_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_clear_timestamp_reg_mem0_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_clear_timestamp_reg_mem1_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_clear_timestamp_reg_mem2_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_clear_timestamp_reg_mem3_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_dac_fifo_unf_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_late_flag_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_num_of_stored_frames_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless