ADC FIFO timestamp enablerΒΆ

TerosHDL

Entity: adc_fifo_timestamp_enabler

  • File: adc_fifo_timestamp_enabler.vhd

Diagram

integer PARAM_DMA_LENGTH_WIDTH boolean PARAM_BYPASS boolean PARAM_DEBUG boolean PARAM_FREERUN boolean PARAM_TWO_ANTENNA_SUPPORT boolean PARAM_x1_FPGA_SAMPLING_RATIO std_logic ADCxN_clk std_logic ADCxN_reset std_logic ADC_clk_division std_logic s_axi_aclk std_logic s_axi_aresetn std_logic_vector(63 downto 0) current_lclk_count std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0) DMA_x_length std_logic DMA_x_length_valid std_logic adc_enable_0 std_logic adc_valid_0 std_logic_vector(15 downto 0) adc_data_0 std_logic adc_enable_1 std_logic adc_valid_1 std_logic_vector(15 downto 0) adc_data_1 std_logic adc_enable_2 std_logic adc_valid_2 std_logic_vector(15 downto 0) adc_data_2 std_logic adc_enable_3 std_logic adc_valid_3 std_logic_vector(15 downto 0) adc_data_3 std_logic ADC_FSM_status_read std_logic_vector(15 downto 0) current_num_samples_o std_logic fwd_adc_enable_0 std_logic fwd_adc_valid_0 std_logic_vector(15 downto 0) fwd_adc_data_0 std_logic fwd_adc_enable_1 std_logic fwd_adc_valid_1 std_logic_vector(15 downto 0) fwd_adc_data_1 std_logic fwd_adc_enable_2 std_logic fwd_adc_valid_2 std_logic_vector(15 downto 0) fwd_adc_data_2 std_logic fwd_adc_enable_3 std_logic fwd_adc_valid_3 std_logic_vector(15 downto 0) fwd_adc_data_3 std_logic fwd_adc_overflow std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0) fwd_DMA_x_length std_logic fwd_DMA_x_length_valid std_logic fwd_adc_overflow_BBclk std_logic fwd_sync_out std_logic_vector(31 downto 0) ADC_FSM_status std_logic ADC_FSM_new_status

Description

Whereas a configuration up to 2x2 (i.e., 4 channels) is supported, the basic functionality of the block needs to work for the most reduced possible configuration (i.e., 1x1 or 2 channels, as provided by AD9364). Hence, even if it is not optimum, the provision of the synhronization header and timestamp value will always use two single DAC channels (i.e., 32 bits or i0 & q0) and, thus, require eight clock cycles to be completed.

The design assumes that 'DMA_x_length_valid' will be always asserted at least one clock cycle before the data associated to that DMA transfer enters this block.

In case of a x1 ratio between the FPGA baseband (ADCxN_clk) and the sampling clocks, the forwarded outputs will be translated from the baseband clock to the AXI one; in such cases, the design assumes that the ratio between the baseband clock and the AXI one is large enough to enable the insertion of the 8 header samples.

Generics

Generic name Type Value Description
PARAM_DMA_LENGTH_WIDTH integer 24 Defines the width of transfer length control register in bits; limits the maximum length of the transfers to 2^PARAM_DMA_LENGTH_WIDTH (e.g., 2^24 = 16M).
PARAM_BYPASS boolean false The block can be bypassed, resulting thus in an unmodified ADI firmware implementation [not implemented for x1 FPGA/sampling clock ratios].
PARAM_DEBUG boolean false The block can be set in 'debug' mode, which will result in 'fwd_adc_data_0' returning a predefined data sequence (i.e., a counter) that enables debugging (e.g., see if samples are lost) [not implemented for x1 FPGA/sampling clock ratios].
PARAM_FREERUN boolean false The block can be set in 'freerun' (i.e., once the first 'x_length' is received, the DMA will be always feed, not checking for new requests as it will be assumed that the PS will be always in time or realigning packets as needed) or in 'burst' mode (i.e., PARAM_FREERUN = false; data will only be provided to the DMA when there is a new request from the PS) [not implemented for x1 FPGA/sampling clock ratios].
PARAM_TWO_ANTENNA_SUPPORT boolean false Defines wether adc_X_2/3' ports are active (true) or not (false [default]).
PARAM_x1_FPGA_SAMPLING_RATIO boolean false Defines whether the baseband FPGA clock (ADCxN_clk) has an actual x1 ratio to the sampling clock (true) or not (false [default]); in the first case, forwarded outputs will be @ADCxN_clk, otherwise @s_axi_aclk

Ports

Port name Direction Type Description
ADCxN_clk in std_logic ADC clock signal xN [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz].
ADCxN_reset in std_logic [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADC_clk_division in std_logic Indicates the division factor between the sampling clock and input clock (i.e., '1' indicates N = 2 or 1x1, '0' indicates N = 4 or 2x2)
s_axi_aclk in std_logic AXI clock signal (@100 MHz)
s_axi_aresetn in std_logic AXI low-active reset signal (mapped to the AXI clock domain [@100 MHz])
current_lclk_count in std_logic_vector(63 downto 0) Current ADC clock cycle (i.e., current I/Q sample count) [@ADCxN_clk, even though the clock-ticks are based on @ADC_clk]
DMA_x_length in std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0) Signal indicating the number of samples comprising the current DMA transfer [@ADCxN_clk]
DMA_x_length_valid in std_logic Valid signal for 'DMA_x_length' [@ADCxN_clk]
adc_enable_0 in std_logic Enable signal for ADC data port 0.
adc_valid_0 in std_logic Valid signal for ADC data port 0.
adc_data_0 in std_logic_vector(15 downto 0) ADC parallel data port 0 [16-bit I samples, Rx antenna 1].
adc_enable_1 in std_logic Enable signal for ADC data port 1.
adc_valid_1 in std_logic Valid signal for ADC data port 1.
adc_data_1 in std_logic_vector(15 downto 0) ADC parallel data port 1 [16-bit Q samples, Rx antenna 1].
adc_enable_2 in std_logic Enable signal for ADC data port 2.
adc_valid_2 in std_logic Valid signal for ADC data port 2.
adc_data_2 in std_logic_vector(15 downto 0) ADC parallel data port 2 [16-bit I samples, Rx antenna 2].
adc_enable_3 in std_logic Enable signal for ADC data port 3.
adc_valid_3 in std_logic Valid signal for ADC data port 3.
adc_data_3 in std_logic_vector(15 downto 0) ADC parallel data port 3 [16-bit Q samples, Rx antenna 2].
current_num_samples_o out std_logic_vector(15 downto 0) Debug-only output port. Forwarding of 'current_num_samples' for debugging reasons.
fwd_adc_enable_0 out std_logic Enable signal for ADC data port 0.
fwd_adc_valid_0 out std_logic Valid signal for ADC data port 0.
fwd_adc_data_0 out std_logic_vector(15 downto 0) ADC parallel data port 0 [16-bit I samples, Rx antenna 1].
fwd_adc_enable_1 out std_logic Enable signal for ADC data port 1.
fwd_adc_valid_1 out std_logic Valid signal for ADC data port 1.
fwd_adc_data_1 out std_logic_vector(15 downto 0) ADC parallel data port 1 [16-bit Q samples, Rx antenna 1].
fwd_adc_enable_2 out std_logic Enable signal for ADC data port 2.
fwd_adc_valid_2 out std_logic Valid signal for ADC data port 2.
fwd_adc_data_2 out std_logic_vector(15 downto 0) ADC parallel data port 2 [16-bit I samples, Rx antenna 2].
fwd_adc_enable_3 out std_logic Enable signal for ADC data port 3.
fwd_adc_valid_3 out std_logic Valid signal for ADC data port 3.
fwd_adc_data_3 out std_logic_vector(15 downto 0) ADC parallel data port 3 [16-bit Q samples, Rx antenna 2].
fwd_adc_overflow out std_logic Overflow signal indicating that the DMA request was late.
fwd_DMA_x_length out std_logic_vector(PARAM_DMA_LENGTH_WIDTH-1 downto 0) Signal indicating the number of samples comprising the current DMA transfer [@s_axi_aclk; only used in case of x1 ratio between FPGA and sampling clocks]
fwd_DMA_x_length_valid out std_logic Valid signal for 'DMA_x_length' [@s_axi_aclk; only used in case of x1 ratio between FPGA and sampling clocks]
fwd_adc_overflow_BBclk out std_logic Overflow signal indicating that the DMA request was late [@ADCxN_clk; only used in case of x1 ratio between FPGA and sampling clocks]
fwd_sync_out out std_logic
ADC_FSM_status out std_logic_vector(31 downto 0) Status register for the FSM controlling the ADC forwarding chain
ADC_FSM_new_status out std_logic Valid signal for 'ADC_FSM_status'
ADC_FSM_status_read in std_logic ACK signal for 'ADC_FSM_status'