Currently only one Tx antenna is supported in this design; this block will interface the rfdc IP and provide the decimated I/Q data, jointly with the related clock, as expected by the timestamping and synchronization blocks.
Generics
Generic name
Type
Value
Description
PARAM_OUT_CLEANING_FIR
boolean
false
A low-pass filter to clean the output signal can be added at the end (true) or skipped [(false) default]
Ports
Port name
Direction
Type
Description
s_axi_aclk
in
std_logic
s_axi_aresetn
in
std_logic
rfdc_N_FFT_param
in
std_logic_vector(2 downto 0)
Signal providing the 'N_FFT' PSS parameter (i.e., number of FFT points) (@s_axi_aclk)
rfdc_N_FFT_valid
in
std_logic
Signal indicating if the output 'N_FFT' PSS parameter is valid (@s_axi_aclk)
dac0_axis_aclk
in
std_logic
DAC channel 0 clock signal (@245.76 MHz)
dac0_axis_aresetn
in
std_logic
RFdc low-active reset signal (mapped to the DAC channel 0 clock domain [@245.76 MHz])
dac00_axis_tdata
out
std_logic_vector(31 downto 0)
Parallel (interleaved) output I/Q data (AXI-formatted)
dac00_axis_tvalid
out
std_logic
Valid signal for 'DAC00_axis_tdata'
dac00_axis_tready
in
std_logic
Signal indicating to RFdc that we are ready to receive new data through 'DAC00_axis_tdata'
DACxN_clk
in
std_logic
DAC clock signal xN [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
DACxN_reset
in
std_logic
DAC high-active reset signal (mapped to the DAC clock xN domain [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
DACxN_locked
in
std_logic
DAC clock locked indication signal
dac_enable_0
in
std_logic
Enable signal for DAC data port 0
dac_valid_0
in
std_logic
Valid signal for DAC data port 0
dac_data_0
in
std_logic_vector(15 downto 0)
DAC parallel data port 0 [16-bit I samples, Tx antenna 1]
dac_enable_1
in
std_logic
Enable signal for DAC data port 1
dac_valid_1
in
std_logic
Valid signal for DAC data port 1
dac_data_1
in
std_logic_vector(15 downto 0)
DAC parallel data port 1 [16-bit Q samples, Tx antenna 1]