Timestamp unit lclk countΒΆ

TerosHDL

Entity: timestamp_unit_lclk_count

  • File: timestamp_unit_lclk_count.vhd

Diagram

integer PARAM_CLOCK_RATIO std_logic ADCxN_clk std_logic ADCxN_reset std_logic ADC_clk_division std_logic_vector(63 downto 0) current_lclk_count

Generics

Generic name Type Value Description
PARAM_CLOCK_RATIO integer 2

Ports

Port name Direction Type Description
ADCxN_clk in std_logic ADC clock signal xN [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADCxN_reset in std_logic ADC high-active reset signal (mapped to the ADC clock xN domain [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADC_clk_division in std_logic Indicates the division factor between the sampling clock and input clock (i.e., '1' indicates N = 2 or 1x1, '0' indicates N = 4 or 2x2)
current_lclk_count out std_logic_vector(63 downto 0) Current ADC clock cycle (i.e., current I/Q sample count)