ADC timestamp enabler packetizerΒΆ

TerosHDL

Entity: adc_timestamp_enabler_packetizer

  • File: adc_timestamp_enabler_packetizer.vhd

Diagram

integer c_AXI_ADDR_WIDTH integer c_AXIS_NOF_CHANNELS std_logic ADCxN_clk std_logic ADCxN_reset std_logic ADC_clk_division std_logic_vector(63 downto 0) current_lclk_count std_logic adc_valid_0 std_logic_vector(15 downto 0) adc_data_0 std_logic adc_valid_1 std_logic_vector(15 downto 0) adc_data_1 std_logic adc_valid_2 std_logic_vector(15 downto 0) adc_data_2 std_logic adc_valid_3 std_logic_vector(15 downto 0) adc_data_3 std_logic axi_aclk std_logic axi_aresetn std_logic_vector(c_AXI_ADDR_WIDTH - 1 downto 0) s_axi_awaddr std_logic_vector(2 downto 0) s_axi_awprot std_logic s_axi_awvalid std_logic_vector(31 downto 0) s_axi_wdata std_logic_vector(3 downto 0) s_axi_wstrb std_logic s_axi_wvalid std_logic_vector(c_AXI_ADDR_WIDTH - 1 downto 0) s_axi_araddr std_logic_vector(2 downto 0) s_axi_arprot std_logic s_axi_arvalid std_logic s_axi_rready std_logic s_axi_bready std_logic m_axis_tready std_logic_vector(1 downto 0) nof_adc_dma_channels std_logic s_axi_awready std_logic s_axi_wready std_logic s_axi_arready std_logic_vector(31 downto 0) s_axi_rdata std_logic_vector(1 downto 0) s_axi_rresp std_logic s_axi_rvalid std_logic_vector(1 downto 0) s_axi_bresp std_logic s_axi_bvalid std_logic_vector(2 * c_AXIS_NOF_CHANNELS * 32 - 1 downto 0) m_axis_tdata std_logic m_axis_tvalid std_logic m_axis_tlast std_logic data_fifo_rstn

Description

Whereas a configuration up to 2x2 (i.e., 4 channels) is supported, the basic functionality of the block needs to work for the most reduced possible configuration (i.e., 1x1 or 2 channels, as provided by AD9364). Hence, even if it is not optimum, the provision of the synhronization header and timestamp value will always use two single DAC channels (i.e., 32 bits or i0 & q0) and, thus, require eight clock cycles to be completed.

Generics

Generic name Type Value Description
c_AXI_ADDR_WIDTH integer 16
c_AXIS_NOF_CHANNELS integer 1

Ports

Port name Direction Type Description
ADCxN_clk in std_logic ADC clock signal xN [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADCxN_reset in std_logic ADC high-active reset signal (mapped to the ADC clock xN domain [depends on antenna (N = 2 for 1x1 and N = 4 for 2x2) configuration and sampling freq; max LTE value for 1x1 is @61.44 MHz and for 2x2 is @122.88 MHz]
ADC_clk_division in std_logic Indicates the division factor between the sampling clock and input clock (i.e., '1' indicates N = 2 or 1x1, '0' indicates N = 4 or 2x2)
current_lclk_count in std_logic_vector(63 downto 0) Current ADC clock cycle (i.e., current I/Q sample count) [@ADCxN_clk, even though the clock-ticks are based on @ADC_clk]
adc_valid_0 in std_logic Valid signal for ADC data port 0
adc_data_0 in std_logic_vector(15 downto 0) ADC parallel data port 0 [16-bit I samples, Rx antenna 1]
adc_valid_1 in std_logic Valid signal for ADC data port 1
adc_data_1 in std_logic_vector(15 downto 0) ADC parallel data port 1 [16-bit Q samples, Rx antenna 1]
adc_valid_2 in std_logic Valid signal for ADC data port 2
adc_data_2 in std_logic_vector(15 downto 0) ADC parallel data port 2 [16-bit I samples, Rx antenna 2]
adc_valid_3 in std_logic Valid signal for ADC data port 3
adc_data_3 in std_logic_vector(15 downto 0) ADC parallel data port 3 [16-bit Q samples, Rx antenna 2]
nof_adc_dma_channels out std_logic_vector(1 downto 0) Number of ADC channels forwarded to a DMA IP
axi_aclk in std_logic
axi_aresetn in std_logic
s_axi_awaddr in std_logic_vector(c_AXI_ADDR_WIDTH - 1 downto 0)
s_axi_awprot in std_logic_vector(2 downto 0)
s_axi_awvalid in std_logic
s_axi_awready out std_logic
s_axi_wdata in std_logic_vector(31 downto 0)
s_axi_wstrb in std_logic_vector(3 downto 0)
s_axi_wvalid in std_logic
s_axi_wready out std_logic
s_axi_araddr in std_logic_vector(c_AXI_ADDR_WIDTH - 1 downto 0)
s_axi_arprot in std_logic_vector(2 downto 0)
s_axi_arvalid in std_logic
s_axi_arready out std_logic
s_axi_rdata out std_logic_vector(31 downto 0)
s_axi_rresp out std_logic_vector(1 downto 0)
s_axi_rvalid out std_logic
s_axi_rready in std_logic
s_axi_bresp out std_logic_vector(1 downto 0)
s_axi_bvalid out std_logic
s_axi_bready in std_logic
m_axis_tdata out std_logic_vector(2 * c_AXIS_NOF_CHANNELS * 32 - 1 downto 0) Double the necessary width to support the required throughput
m_axis_tready in std_logic
m_axis_tvalid out std_logic
m_axis_tlast out std_logic
data_fifo_rstn out std_logic

Instantiations

  • synchronizer_DMA_packet_length_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_data_fwd_enable_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_data_fifo_reset_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_DMA_packet_length_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless
  • synchronizer_current_data_fwd_enable_ins: work.multibit_cross_clock_domain_fifo_synchronizer_resetless