DAC DMAC xlength snifferΒΆ

TerosHDL

Entity: dac_dmac_xlength_sniffer

  • File: dac_dmac_xlength_sniffer.vhd

Diagram

integer DMA_LENGTH_WIDTH std_logic s_axi_aclk std_logic s_axi_aresetn std_logic s_axi_awvalid std_logic_vector(11 downto 0) s_axi_awaddr std_logic s_axi_wvalid std_logic_vector(31 downto 0) s_axi_wdata std_logic s_axi_bready std_logic fwd_s_axi_awready std_logic fwd_s_axi_wready std_logic fwd_s_axi_bvalid std_logic_vector(DMA_LENGTH_WIDTH-1 downto 0) DMA_x_length std_logic DMA_x_length_valid

Description

This block will sniff the current value of 'x_length', but it will not modify it in any way. Hence, it assumes that the SW running in the PS has requested 8 extra bytes to accommodate the (64-bit) timestamp (i.e., 'x_length' is N+7 bytes, instead of the N-1 value described in the original ADI's 'axi_dmac' documentation).

Generics

Generic name Type Value Description
DMA_LENGTH_WIDTH integer 24 defines the width of transfer length control register in bits; limits the maximum length of the transfers to 2^DMA_LENGTH_WIDTH (e.g., 2^24 = 16M)

Ports

Port name Direction Type Description
DMA_x_length out std_logic_vector(DMA_LENGTH_WIDTH-1 downto 0) Signal indicating the number of samples comprising the current DMA transfer
DMA_x_length_valid out std_logic Valid signal for 'DMA_x_length'
s_axi_aclk in std_logic
s_axi_aresetn in std_logic
s_axi_awvalid in std_logic
s_axi_awaddr in std_logic_vector(11 downto 0)
s_axi_wvalid in std_logic
s_axi_wdata in std_logic_vector(31 downto 0)
s_axi_bready in std_logic
fwd_s_axi_awready in std_logic
fwd_s_axi_wready in std_logic
fwd_s_axi_bvalid in std_logic