DMA depack channelsΒΆ

TerosHDL

Entity: dma_depack_channels

  • File: dma_depack_channels.vhd

Diagram

integer PARAM_CHANNEL_WIDTH integer PARAM_NUM_CHANNELS std_logic s_axi_aclk std_logic s_axi_aresetn std_logic_vector(PARAM_NUM_CHANNELS*PARAM_CHANNEL_WIDTH-1 downto 0) axis_in_tdata std_logic axis_in_tvalid std_logic axis_in_tlast std_logic axis_in_tready std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0) dac_data_0 std_logic dac_data_0_valid std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0) dac_data_1 std_logic dac_data_1_valid std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0) dac_data_2 std_logic dac_data_2_valid std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0) dac_data_3 std_logic dac_data_3_valid

Generics

Generic name Type Value Description
PARAM_CHANNEL_WIDTH integer 16 Width of each channel
PARAM_NUM_CHANNELS integer 2 Default is 2, i.e. I and Q for one antenna

Ports

Port name Direction Type Description
s_axi_aclk in std_logic
s_axi_aresetn in std_logic
axis_in_tdata in std_logic_vector(PARAM_NUM_CHANNELS*PARAM_CHANNEL_WIDTH-1 downto 0)
axis_in_tvalid in std_logic
axis_in_tlast in std_logic
axis_in_tready out std_logic
dac_data_0 out std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0)
dac_data_0_valid out std_logic
dac_data_1 out std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0)
dac_data_1_valid out std_logic
dac_data_2 out std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0)
dac_data_2_valid out std_logic
dac_data_3 out std_logic_vector(PARAM_CHANNEL_WIDTH-1 downto 0)
dac_data_3_valid out std_logic